Semiconductor manufacture is becoming an increasingly automated process requiring precise methods of process control to ensure a quality output. A wafer of a semiconductor chip is typically manufactured by etching the desired pattern in a low-dielectric constant (“Low-K”) film and then filling the etched line, or trench, with first a thin layer of barrier material, typically 100 angstroms thick. The remainder of the trench is then filled with a conductive material, such as copper. In order to insure that all of the lines are uniformly filled, the line and the field area (i.e., the surface of the semiconductor wafer) are filled/covered with more barrier material and copper than is necessary, which leaves an excess of barrier material and copper on the surface of the Low-K film. Typical excess may consist of a 250 angstrom thick layer of barrier topped with an 8000 angstrom thick layer of copper.
Semiconductor chips are commonly fabricated from multiple stacked layers of materials on a semiconductor wafer. In small devices, for example 130 nm, 90 nm, and/or 65 nm devices, a thin dielectric anti-reflective coating (“DARC”) layer, typically 500-600 angstroms, is deposited on top of the Low-K film between each successive layer. More specifically, the DARC layer is deposited directly on the field area of the semiconductor wafer, etched, and is then covered with barrier and copper. The DARC layer helps to reduce reflections from the reflection of light from metal, e.g., copper, embedded in the previous level of the semiconductor wafer.
For example, while performing a lithography patterning process on one level of wafer, whereby the etch pattern for the wafer is imprinted on the wafer, reflection from the copper in the preceding level of wafer can cause interference with the lithography tool. The lithography tool determines when lithography patterning on a portion of the wafer is completed by analyzing the light reflecting from that portion of the wafer. Reflected light from a previous level of wafer may convince the lithography tool that it has finished patterning that portion of the current wafer before the process has actually finished. Consequently, the DARC layer helps to minimize such interference and, thus, facilitate the lithography step.
One of the subsequent steps in a typical process involving copper is then to polish off the barrier material and copper and to then continue polishing off the DARC layer using a polishing, e.g., chemical-mechanical polishing (CMP) process. Ideally, the polishing process must stop at the transition interface between the DARC and a second dielectric film, which is the Low-K film. The final thickness of the Low-K film after polishing is complete is an indication of how much copper or metal is remaining in the line (the Low-K film having been etched and filled with copper).
Polishing away too much of the Low-K film, and, hence, too much of the copper in the line, affects at least two properties of the semiconductor wafer. First, the thickness of the Low-K film, which is proportional to the amount of copper in the line, determines the resistance of the line, where the lower the resistance the faster the device. If too much copper is removed, the effective resistance increases. Secondly, the Low-K film thickness determines the interlayer capacitance, where the lower the interlayer capacitance, the faster the device. If too much of the Low-K film is removed from the line, the interlayer capacitance increases. Thus, removing too much of the Low-K film lowers the effective speed of the device for both of the aforementioned reasons.
Since the thickness of the Low-K film affects the performance of semiconductor wafer devices, it is desirable to precisely maintain the thickness of the Low-K film from wafer to wafer. The Low-K film thickness that is required to be maintained to preserve, for example, the speed of the device, actually is part of the chip design. If the appropriate thickness of the Low-K film, and, thus, the amount of copper in the line, is not attained, then the semiconductor device will not achieve the desired performance. Therefore, it is important to reach the target for the thickness for the Low-K film and the copper in the line, as per the design specifications of the semiconductor wafer.
One current method of determining an endpoint, or the point at which the polishing process should be terminated, is based on polish time, which is a timed process. In the timed process, it is empirically determined how much time is required to polish off the copper, the barrier, and DARC film. This time could be set at any value, for example, forty seconds, thirty seconds, etc. The desire is to polish off as little of the Low-K film as is possible. However, when a wafer is polished, all surfaces of the wafer are not polished uniformly. As a result, there is a gradient in the surface of the wafer. Therefore, to insure that no residues are left on the surface of the wafer, more of the wafer is polished than is necessary, resulting in the loss of some Low-K film.
Another problem with the timed approach is that any slight shift in the material property of the barrier, DARC film, and/or the Low-K film affects the polish removal rate, and thus the amount of material that is removed within the predetermined time interval. Another factor effecting a change in the polish removal rate is the lack of consistency in CMP processes in the consumables, for example, the slurry and/or the pad. In effect, any change in the polish removal rate can affect the amount of Low-K film removed during the polishing process and may lead to too little or too much of the Low-K film being removed.
What is desired is an endpoint detection scheme that enables the polish process to be terminated at the transition interface between the overlying material and the Low-K layer of a semiconductor wafer such that little material in the Low-K layer of the wafer is removed.